The present invention relates in general to computer aided circuit design, and in particular to a system for modeling and estimating crosstalk noise and detecting false logic.
In electrical circuits, crosstalk noise is generated when signal activity on one signal conductor network ("net") couples as noise to neighboring signal nets through parasitic capacitances. With the dramatic increase in VLSI chip gate counts and circuit density, crosstalk noise has become a critical issue when designing integrated circuits. Thus, it is important for a Computer Aided Design (CAD) tool to simulate and predict circuit behavior taking into account interference due to such noise.
Crosstalk noise, being capacitively coupled in nature, is most significant at the instant when the interfering sources (culprits) are fast switching, thereby coupling the signal waveforms to the victim via some parasitic coupling capacitance. This noise may sometimes cause false logic to occur.
Although SPICE circuit simulation may be used to evaluate crosstalk noise, such evaluation requires a considerable amount of time and processing power. Depending upon the complexity of the circuit analyzed and capacity of the CAD system used, SPICE crosstalk analysis might take weeks to complete. Accordingly, there is a need for an improved CAD tool capable of providing fast and reasonably accurate estimates of crosstalk noise.